Our CTO Krzysztof and Senior FPGA developer Mateusz have presented an article at the FPGA Conference Europe in Munich
#highspeed, #FPGA, #forum, #Munich, #SpinalHDL
The title of the presentation was:
Optimizing FPGA Systems: A Case Study of employing SpinalHDL and VexRISCV core in Commercial Application.
Abstract:
In this presentation, we dive into our active exploration of the application of SpinalHDL capabilities within commercial projects, with a specific focus on integrating VexRISCV – an implementation of the RISC-V architecture CPU utilizing the SpinalHDL/Scala language. We begin by introducing a case of the existing implementation of a product in an optical sensing industry. We highlight its inefficiencies, which stem from centralized computations using CUDA based acceleration for signal demodulation. These limitations restrict the scalability of the whole system due to computational constraints. Despite challenges posed by existing hardware implementation of data acquisition cards and limited FPGA resources, our objective is to decentralize computations to enhance system scalability so a higher number of acquisition cards can be employed by the system. We provide an overview of SpinalHDL and its Scala-based language, emphasizing its relevance in our project. Our goal is to transfer significant parts of computations into small FPGA chips accompanying ADCs, necessitating a highly configurable CPU architecture, for which we explore the potential of SpinalHDL/VexRISCV due to its pointed out flexibility. We discuss VexRISCV’s architecture and its implementation approach, along with customization possibilities, such as integrating custom CPU architecture “plugins”. We are addressing the limitation of legacy communication protocol by implementing a custom Boot Manager around the VexRISCV CPU ensuring seamless integration with the existing system. Finally, we present the outcomes of our project, including the successful offloading of CUDA cores by transferring the signal demodulation algorithm to acquisition cards, and share insights from using SpinalHDL/VexRISCV in a commercial setting, highlighting encountered challenges and potential areas for improvement.
A few words about SpinalHDL
SpinalHDL is an Open Source project started by Charles Papon in December 2014. We have been using it since 2021 to speed up some of our FPGA development. It’s an efficient way of describing hardware: no need to deal with implementation details. Time-boost you gain could be impressive.
Some of the advantages that SpinalHDL gives:
- There is no logic overhead in the generated code.
- SpinalHDL is interoperable with VHDL and Verilog.
- Simulation using Verilator enables simulation of not only your design, but also testing of firmware running in simulated design.
- Large SpinalHDL standard library.
- Open-source tool with licensing scheme enabling usage in commercial applications.
- Responsiveness of SpinalHDL’s creator, Charles Papon.
Congratulations once again to Krzysztof and Mateusz on their presentation.
